1. Field of the Invention
The present invention relates to a semiconductor device provided with buried gates. More particularly, it relates to a buried-gate-type semiconductor device of which gate interval is shortened as much as possible so as to enhance channel concentration and lower ON-resistance, and relates to a buried-gate-type semiconductor device that intends to prevent a decline in voltage-resistance caused by local concentration of electrical field around bottom portion of gates. The inventive buried-gate-type semiconductor device is efficient especially to a high voltage-resistance power semiconductor device.
2. Description of Related Art
There have conventionally been used buried-gate-type semiconductor devices for power supply and the like (e.g., an insulated-gate-type bipolar transistor disclosed in JP Laid-open Patent Publication No. 2002-100770). Some of conventional buried-gate-type semiconductors of this kind are of stripe type in which zonal buried gates are arranged in parallel to one another. FIG. 50 and FIG. 51 show an example of a stripe type. FIG. 51 is a sectional view of portion A—A in FIG. 50. FIG. 50 is a sectional view of portion E—E in FIG. 51. This buried-gate-type semiconductor device has trench-type gate electrodes. The buried-gate-type semiconductor device generally structured such that source regions and gate electrodes are arranged on a surface side of its semiconductor substrate (an upper surface in FIG. 51) and a drain region and the like are arranged on other surface side of the substrate (a lower surface in FIG. 51).
That is, trench-type gate electrodes 906, P+ source regions 900 and N+ source regions 904 are arranged on the upper surface side of the semiconductor substrate. Gate electrodes 906 are insulated from the semiconductor substrate by gate dielectrics 905 and an interlayer dielectric 907. On the above of those, there are arranged a source electrode 909. The source electrode 909 is in contact with the semiconductor substrate at zonal contact openings 908 in parallel to gate electrodes 906. Thereby, the source electrode 909 is in contact with both P+ source regions 900 and N+ source regions 904. Beneath P+ source regions 900 and N+ source regions 904, there are arranged P channel regions 903. The bottom level of P channel regions 903 is shallower than that of gate electrodes 906.
Beneath P channel regions 903, there is formed an N drift region 902. Most part of the N drift region 902 is deeper than the bottom level of gate electrodes 906 and extends to almost entirety of the semiconductor substrate. Further beneath the N drift region 902, there is arranged a P+ drain region 901. There is formed a drain electrode 910 in contact with the P+ drain region 901 further beneath it. In this buried-gate-type semiconductor device, a range indicated with an arrow Y in FIG. 50 corresponds to a unit repeated in a vertical direction in FIG. 50. Furthermore, a range indicated with an arrow X in FIG. 50 corresponds to a unit repeated in a horizontal direction in FIG. 50. A unit X repeated in a horizontal direction is a sum of a range 906W occupied by a gate electrode 906 and gate dielectric 905 and a range 906S occupied by an N+ source region 904 and the like.
FIG. 52 and FIG. 53 show another example of a buried-gate-type semiconductor device of this kind. The buried-gate-type semiconductor device shown in FIG. 52 and FIG. 53 is a variant of the buried-gate-type semiconductor device directed to FIG. 50 and FIG. 51. That is, gate electrode 906 is formed in cross striped shape in plane sectional view. A quadrangle-shaped contact opening 908 is arranged on center of each square and furthermore, a P+ source region 900 is made to be in contact with a source electrode 909 at the center of a contact opening 908. Out of section of a portion A—A of this buried-gate-type semiconductor device directed to FIG. 52, a range indicated with an arrow K is same as FIG. 51. FIG. 53 is an elevation sectional view of portion H—H in FIG. 52.
FIG. 54 shows another conventional semiconductor device details of which are a little different from the buried-gate type semiconductor devices shown in FIG. 50 through FIG. 53. The semiconductor device directed to FIG. 54 includes P+ gate regions 800 arranged within its semiconductor substrate. That is, this semiconductor device is not an insulated-gate type but a junction-gate type.
However, the buried-gate-type semiconductor device directed to FIG. 50 and FIG. 51 has the following problems. That is, enhancement of channel concentration is limited. This is because intervals 906S between adjoining gate electrodes 906 cannot be made so small. In this semiconductor device, zonal contact openings 908 are arranged between adjoining gate electrodes 906 and a P+ source region 900 is arranged within each contact opening 908. Therefore, an interval 906S needs a distance that is same as or lager than a sum of: two mating allowances 900M for a P+ source region 900 and a contact opening 908 arranged at both sides of a 900W, a width of a P+ source region 900 itself; and two mating allowance 906M for a contact opening 908 and a gate dielectric 905. Therefore, a minimum dimension of an interval 906S between adjoining gate electrodes 906 is large. This aspect limits enhancement of channel concentration, i.e., lowering of ON-resistance. Furthermore, in case gate electrodes 906 and the source electrode 909 are short-circuited and voltage is applied to the drain electrode 910 with reference to the short-circuited electrodes, electrical field concentrates at shoulder portions, cross portions of bottom surfaces and side surfaces of gate electrodes 906 (an arrow L in FIG. 51). Therefore, voltage-resistance lowers, which is problematic.
This kind of problem is even more serious for a semiconductor device directed to FIG. 52 and FIG. 53 that has a cross striped gate electrode 906. This is because depth at crossing portions of a gate electrode 906 is deeper than other portions of that, as apparent from the elevation sectional view of FIG. 53. Therefore, concentration of electrical fields is more intense at crossing portions of a gate electrode 906. Due to manufacturing process reason, it is inevitable for a gate electrode 906 which has such crossing portions to have such convex shape at its bottom surface. That is, etching gas for digging trenches is supplied to crossing portions of which effective width is wide more than to other portion.
Voltage-resistance is not so problematic for a junction-type semiconductor device as shown in FIG. 54. However, there is another problem such that normally-OFF characteristic cannot be obtained by voltage control for a junction-type semiconductor device. That is, in case positive voltage is applied to P+ gate regions 800 not insulated, holes are injected to the N drift region 802 from P+ gate regions 800. As a result, current flows between a source electrode 809 and a drain electrode 810. Therefore, current control is required for such a semiconductor device to obtain normally-OFF characteristic.